General Background Art of the Present Invention
Conventionally, top gated thin film transistors (TFTs) in which polysilicon is used as a semiconductor have typically been used for semiconductor devices, especially for pixel switching elements for use in liquid crystal display devices.
A cross-sectional view of a conventional top gated thin film transistor for use in a semiconductor device is shown in FIG. 1. This thin film transistor, although being a prior art device, will be described below with reference to FIG. 1 since this thin film transistor is related to the present invention.
In FIG. 1, reference numeral 1 denotes a glass substrate. Reference numeral 2 denotes an undercoat layer formed over the upper surface of the glass substrate. Reference numeral 3 denotes a polysilicon layer that is formed over the upper surface of the undercoat layer at a prescribed position and forms a channel region in a semiconductor layer. Reference numeral 4 denotes a polysilicon layer which likewise forms a source region. Reference numeral 5 denotes a polysilicon layer which likewise forms a drain region. Reference numerals 34 and 35 denote polysilicon layers which likewise form LDD (Lightly Doped Drain) regions. Reference numeral 6 denotes a gate insulating film. Reference numeral 7 denotes a gate line layer positioned above the polysilicon layer which forms the channel region with the gate insulating film interposed therebetween. Reference numeral 8 denotes an interlayer insulating film. Reference numerals 94 and 95 denote a source wiring layer and a drain wiring layer, respectively, that are connected to the source region and the drain region through contact holes formed in the portions corresponding to the source region and the drain region.
A thin film transistor having such a structure in which polysilicon is used has a high mobility of several ten to several hundred cm2/Vs. Therefore, the thin film transistor is widely used for a switching element of a pixel area and as an element in a driving circuit in an active matrix liquid crystal display device.
For a switching element in the pixel area, an n-type polysilicon thin film transistor is generally used, but it shows a large leakage current as it is. In view of this, the LDD regions 34 and 35 having a very small impurity concentration are interposed between the polysilicon layer that forms the channel region and the source and drain regions, which are disposed on opposing sides thereof so that the electric fields at the end portions of the source and drain regions are relaxed and the leakage current is reduced.
Well-known or widely used methods of fabricating a polysilicon thin film include a laser annealing technique in which after (or before) an amorphous silicon layer formed over the undercoat layer is separated (patterned) according to the arrangement of transistor elements on the substrate, the amorphous layer is made to temporarily melt by irradiation with an excimer laser and then is polycrystallized at the time of the solidification and a technique in which an amorphous silicon having an epitaxial growth-promoting agent previously mixed therein is heated to undergo solid-phase growth.
In addition, known methods of forming a source region and a drain region include a technique in which impurities such as phosphorus ions are implanted and then activation is performed using a laser or heat, a self-activated technique in which the effects of hydrogen that is injected for the purpose of dilution at the same time as the ion implantation are exercised, and the like.
The previously-mentioned method that employs a laser for forming a polysilicon layer and for activating a source and drain regions is a process that can be performed at low temperatures and can employ an inexpensive glass substrate. Therefore, this method is extremely useful for mass production of liquid crystal display devices.
In addition, a method that employs a non-mass separation ion doping and a self-activating technique utilizing the advantages thereof for the formation of the source and drain regions is suitable for a process which uses large-sized substrates, and therefore is contemplated as suitable for mass production.
Next, the manner of the process for forming a top gated polysilicon thin film transistor on a substrate using a laser annealing technique and a self-activating technique will be described with reference to FIG. 2.
The present FIG. 2 is a cross-sectional view showing how a semiconductor device, especially a transistor, shown in FIG. 1, is formed with the progress of the manufacturing process.
(1) An undercoat layer 2 of a SiO2 film is formed into a thickness of 600 nm over the upper surface of a glass substrate and an amorphous Si film is formed thereon into a thickness of 50 nm, and then this amorphous Si film is polycrystallized by laser annealing and is patterned into a so-called island-like shape (so as to be separated). (Note that laser annealing may be performed after the patterning of the amorphous Si film. The patterning is generally performed using photolithography and etching.)                (2) A SiO2 film 6 having a thickness of 100 nm is formed over the island-like polysilicon film as a gate insulating film. A gate insulating layer is formed thereon into a thickness of 250 nm and is patterned so as to leave a gate line layer only above a portion that forms a channel region in the semiconductor layer made of the polysilicon film. Subsequently, using the remaining gate line layer as an implantation mask, doping (n−doping) with a small dose of phosphorus ions is carried out from a direction above the substrate so that the polysilicon layer, except a region that is directly below the gate line layer, is made to have the same impurity concentration as LDD regions.        
(3) An implantation mask 10 is formed of a resist such that the implantation mask extends off the opposing sides of the gate line layer by about 15% of the gate line layer width in the direction of the channel. Doping (n+doping) with a large dose of phosphorus ions is carried out from a direction above the substrate, so that in the polysilicon film, regions directly below the resist mask are made LDD regions while regions lying on opposing sides of the LDD regions that are doped with a large dose of phosphorus ions are made a source region and a drain region.
(4) The resist mask is removed and an interlayer insulating film 8 is formed over the entire structure, and then activation is performed for about one hour at 500° C.
(4) Contact holes are formed through portions of the interlayer insulating film and the gate insulating film that correspond to the source region 4 and the drain region 5, and by filling the insides thereof with a metal, a source wiring layer 94 and a drain wiring layer 95 are formed.
With the above process, a thin film transistor (TFT) using polysilicon is completed.
It should be noted that in reality, thin film transistors like those shown in the drawings formed on the substrate are arranged in a plurality of rows and columns so as to correspond to pixels or driving circuits of a display unit, or the substrate itself is arranged in a plurality of layers depending on circumstances, and these necessitate the formation of signal lines and the like for connecting a plurality of thin film transistors; however, since these are known in the art, illustrations and explanations are omitted.
Background Art in View of the Problems that the Present Invention is Going to Solve
In a semiconductor device or a thin film transistor made of polysilicon as a primary portion thereof that is fabricated in such a manner, when a SiO2 film is used as the gate insulating film, the film thickness needs to be large enough to ensure a withstand voltage required for transistor operation between the gate insulating film and the source and drain regions. However, since the stress to the SiO2 film increases, microcracks are likely to be developed at the time of beat treatments such as annealing and forcing out hydrogen after the formation of the film. Moreover, in the case of a large-sized substrate in which each side is 30 cm or more, the stress to the SiO2 film causes the substrate to be warped, and thereby problems are likely to arise in transport in manufacturing equipment, vacuum holding for transportation and positioning, and the like.
When a SiN film or a multilayer film including a SiN film is used as the gate insulating film, the thickness itself of the gate insulating film that is necessary to ensure a withstand voltage required for transistor operation can be smaller in comparison with the case of SiO2. However, the stress to the SiN film is greater than that in the case of a SiO2 film, creating a similar problem. (For reference, the thermal expansion coefficient of SiN is approximately the negative 6th power of 2.8 to 3.2×10/° C., and that of glass is the negative 6th power of 3.8×10/° C.)
Especially, in view of the recent trend toward larger-sized display screens of display devices, substrate size has also increased, and therefore solutions for these problems have been desired.
Aside from the foregoing, there has been a similar problem for an underlying insulating film on the glass substrate. Since this problem is discussed in detail in Japanese Unexamined Patent Publication No. 11-163353, explanations are omitted.
In addition, with the trend toward larger-sized substrates, there is a similar need in a bottom gated thin film transistor.